diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-17 10:34:26 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-24 11:49:15 +0000 |
| commit | c3c55210ee598e2dfcfc0bbe664cd703e6fdf3fe (patch) | |
| tree | 8efb929b92a7c8cfd7cb92042ac628d396e3d6ae /src/soc/amd | |
| parent | 5daa1d38985a19dc84f2299dba2e340dda2870ae (diff) | |
| download | coreboot-c3c55210ee598e2dfcfc0bbe664cd703e6fdf3fe.tar.xz | |
ACPI: Replace smm_setup_structures()
Except for whitespace and varying casts the codes were
the same when implemented.
Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/smi.c | 5 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/smi.c | 5 |
4 files changed, 2 insertions, 10 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 2df0b6a120..fd2a2053fb 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS select UDK_2017_BINDING select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS + select ACPI_NO_SMI_GNVS config MEMLAYOUT_LD_FILE string diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index ba36e65da6..125dde601c 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -11,11 +11,6 @@ #include <soc/southbridge.h> #include <soc/smi.h> -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 47642a9fda..9bb5604391 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select SSE2 select RTC + select ACPI_NO_SMI_GNVS config AMD_APU_STONEYRIDGE bool diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index a3473aafc5..fb6d3484ad 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -10,11 +10,6 @@ #include <soc/southbridge.h> #include <soc/smi.h> -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { |