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authorNico Huber <nico.huber@secunet.com>2019-12-13 17:08:49 +0100
committerNico Huber <nico.h@gmx.de>2019-12-14 15:38:16 +0000
commit7176a54c2b4c1a95219c5ab9e7b7b12a8ab6b0e2 (patch)
tree3c66693664456c59e3bdb75a70790fe8b114355d /src/soc/amd
parent9efc7fc540d3b235274448d986747eab226b999d (diff)
downloadcoreboot-7176a54c2b4c1a95219c5ab9e7b7b12a8ab6b0e2.tar.xz
Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"
This reverts commit 01787608670adec26fcea48173e18395e51c790e. AMD: Dropping the _HID of PCI root bus doesn't work well and people started to notice the breakage. Intel: These platforms have a devicetree switch to choose between PCI and ACPI modes. In the former case we need _ADR, but in the latter _HID as the PCI devices are hidden. The conflicting use of _ADR and _HID still needs to be fixed before we can bump our IASL version. Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/acpi/northbridge.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl
index 09bf2e18c2..fe78534403 100644
--- a/src/soc/amd/stoneyridge/acpi/northbridge.asl
+++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl
@@ -17,7 +17,7 @@
/* Note: Only need HID on Primary Bus */
External (TOM1)
External (TOM2)
-/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */
+Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */