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authorArthur Heymans <arthur@aheymans.xyz>2019-10-23 17:25:58 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-01 11:44:51 +0000
commit340e4b80904feb6c5c21497fc52966854fa5ee79 (patch)
tree4026de0ec0cc41f51dd121a0be76642a8d0a286d /src/soc/cavium/cn81xx
parent44874482fec69a849b06c378aa3eb69e75425256 (diff)
downloadcoreboot-340e4b80904feb6c5c21497fc52966854fa5ee79.tar.xz
lib/cbmem_top: Add a common cbmem_top implementation
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/cavium/cn81xx')
-rw-r--r--src/soc/cavium/cn81xx/cbmem.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c
index bb6fa18f20..a39bf4fe35 100644
--- a/src/soc/cavium/cn81xx/cbmem.c
+++ b/src/soc/cavium/cn81xx/cbmem.c
@@ -20,7 +20,7 @@
#include <stdlib.h>
#include <symbols.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
/* Make sure not to overlap with reserved ATF scratchpad */
return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB);