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| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-08 17:55:26 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-10 20:05:35 +0200 |
| commit | ccd8700cac9bda4229ba5628e6f51ab0b96fde41 (patch) | |
| tree | bc5b8b94337d609de66b31e603b67e1bed0ca0dd /src/soc/intel/apollolake/Kconfig | |
| parent | e7ceae79502705a8dc86943e6296fd2cf7735677 (diff) | |
| download | coreboot-ccd8700cac9bda4229ba5628e6f51ab0b96fde41.tar.xz | |
soc/intel/apollolake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h
Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/Kconfig')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 70d2099605..c1ce9d729e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS # CPU specific options select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC + select PCR_COMMON_IOSF_1_0 select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS @@ -52,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI @@ -91,9 +93,11 @@ config SOC_INTEL_COMMON_RESET bool default y -config IOSF_BASE_ADDRESS - hex "MMIO Base Address of sideband bus" +config PCR_BASE_ADDRESS + hex default 0xd0000000 + help + This option allows you to select MMIO Base Address of sideband bus. config DCACHE_RAM_BASE hex "Base address of cache-as-RAM" |