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authorKane Chen <kane.chen@intel.com>2017-01-11 12:53:58 +0800
committerAaron Durbin <adurbin@chromium.org>2017-01-14 01:17:40 +0100
commit9d490daf8d8327f8f01123cf152edf75474f54ce (patch)
tree3dbb52467489008af011bf35586a81894a701a10 /src/soc/intel/apollolake/chip.h
parente7056a82e098f3d1eb368ef4be021264cb54f20a (diff)
downloadcoreboot-9d490daf8d8327f8f01123cf152edf75474f54ce.tar.xz
soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetree
This code allows people to override the usb2 eye pattern UPD settings for boards. BUG=chrome-os-partner:61031 BRANCH=None TEST=Usb2 function ok and make sure fsp upd is overridden Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/18060 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
-rw-r--r--src/soc/intel/apollolake/chip.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 5f8fed9a56..d60ffbf9f6 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -24,6 +24,7 @@
#include <soc/intel/common/lpss_i2c.h>
#include <device/i2c.h>
#include <soc/pm.h>
+#include <soc/usb.h>
#define CLKREQ_DISABLED 0xf
#define APOLLOLAKE_I2C_DEV_MAX 8
@@ -115,6 +116,10 @@ struct soc_intel_apollolake_config {
/* GPIO pin for PERST_0 */
uint16_t prt0_gpio;
+
+ /* USB2 eye diagram settings per port */
+ struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX];
+
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */