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| author | Furquan Shaikh <furquan@google.com> | 2016-06-19 23:20:43 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-06-21 20:39:32 +0200 |
| commit | 0be3da53c6eb1b4c05a51151c8059fbb4d4024ac (patch) | |
| tree | df28800d0efd5421a503101adefb658797b888d7 /src/soc/intel/apollolake/include | |
| parent | bdcda710a7e4bc439408eedaf3e66145c6831c90 (diff) | |
| download | coreboot-0be3da53c6eb1b4c05a51151c8059fbb4d4024ac.tar.xz | |
intel/apollolake: Calculate BIOS mmap at runtime
Instead of hard-coding the BIOS region start and end addresses, read
BIOS_BFPREG to determine the base and limit for the mapped BIOS
region.
BUG=chrome-os-partner:54563
Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/spi.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h index f67110f125..20e78d7843 100644 --- a/src/soc/intel/apollolake/include/soc/spi.h +++ b/src/soc/intel/apollolake/include/soc/spi.h @@ -28,12 +28,19 @@ #define SPIBAR_BIOS_CONTROL_EISS (1 << 5) /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ +#define SPIBAR_BIOS_BFPREG 0x00 #define SPIBAR_HSFSTS_CTL 0x04 #define SPIBAR_FADDR 0x08 #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) #define SPIBAR_PTINX 0xcc #define SPIBAR_PTDATA 0xd0 +/* Bit definitions and masks for BIOS_BFPREG register. */ +#define SPIBAR_BFPREG_PRB_MASK (0x7fff) +#define SPIBAR_BFPREG_PRL_SHIFT (16) +#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) +#define SPIBAR_BFPREG_SBRS (1 << 31) + /* Bit definitions for HSFSTS_CTL register */ #define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) #define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) |