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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-04 14:51:19 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-27 13:47:11 +0000 |
| commit | b48d63359bb4beb63cf2e14edb7b1d833e602ce1 (patch) | |
| tree | b0afa3995446bc60aca5d8700cf9d43249a431a9 /src/soc/intel/baytrail/include | |
| parent | 4ff63d3a11014fa1a54c82a3023182059c5812f1 (diff) | |
| download | coreboot-b48d63359bb4beb63cf2e14edb7b1d833e602ce1.tar.xz | |
soc/intel/baytrail: Use sb/intel/common/spi.c
This common implementation is compatible.
Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/baytrail/include')
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/spi.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/intel/baytrail/include/soc/spi.h b/src/soc/intel/baytrail/include/soc/spi.h index 063dd7fd3a..1ac0b59e56 100644 --- a/src/soc/intel/baytrail/include/soc/spi.h +++ b/src/soc/intel/baytrail/include/soc/spi.h @@ -20,14 +20,7 @@ /* These registers live behind SPI_BASE_ADDRESS. */ #define HSFSTS 0x04 -#define FDATA0 0x10 # define FLOCKDN (0x1 << 15) -#define SSFS 0x90 -# define CYCLE_DONE_STATUS (0x1 << 2) -# define FLASH_CYCLE_ERROR (0x1 << 3) -#define SSFC 0x91 -# define SPI_CYCLE_GO (0x1 << 1) -# define DATA_CYCLE (0x1 << 14) #define PREOP 0x94 #define OPTYPE 0x96 #define OPMENU0 0x98 |