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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-02 06:13:22 +0300 |
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committer | Martin Roth <martinroth@google.com> | 2019-08-03 17:34:40 +0000 |
commit | 26a682c9441b4f7312ff9f69d22029841aa245bd (patch) | |
tree | 1543a1ae418702e3258f35ab435ea9ad79583ebf /src/soc/intel/baytrail/memmap.c | |
parent | 825646e6431b51bd45349dbd2cb1d607e2eecae1 (diff) | |
download | coreboot-26a682c9441b4f7312ff9f69d22029841aa245bd.tar.xz |
intel/baytrail,broadwell: Move stage cache support function
Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.
Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/memmap.c')
-rw-r--r-- | src/soc/intel/baytrail/memmap.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 211f476712..94e91ca7a1 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -14,6 +14,7 @@ */ #include <cbmem.h> +#include <stage_cache.h> #include <soc/iosf.h> #include <soc/smm.h> @@ -26,3 +27,16 @@ void *cbmem_top(void) { return (void *) smm_region_start(); } + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + *base = &smm_base[smm_region_size() - cache_size]; +} |