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| author | Shaunak Saha <shaunak.saha@intel.com> | 2017-10-04 23:08:40 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-26 15:55:37 +0000 |
| commit | 95b61752dbb56b9a7a2da439c5d21e30643661ef (patch) | |
| tree | b7856619ddeb70752c935f727a46f9779f8dae0d /src/soc/intel/cannonlake/chip.c | |
| parent | 66b5acc54bf75b186efea431dfac6eebce527403 (diff) | |
| download | coreboot-95b61752dbb56b9a7a2da439c5d21e30643661ef.tar.xz | |
soc/intel/cannonlake: Add support for C state and P state
This patch adds the C state and P state configurations for
cannonlake soc.
TEST = Boot and test the CPU states for all the cores are
present in "powertop" tool output.
Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.c')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 23e6fffbe8..2810ed11f5 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -154,6 +154,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void soc_enable(device_t dev) |