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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:24:54 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-24 17:05:06 +0200 |
| commit | 0946ec37aa4660ecf16d66cb1174a68df0afc4f0 (patch) | |
| tree | 7be11b3d97f09f9f5fd176b275d0df3a9c2692e4 /src/soc/intel/common/Makefile.inc | |
| parent | 4a8c19cc90464ad215395bd116c9dc95fc682cac (diff) | |
| download | coreboot-0946ec37aa4660ecf16d66cb1174a68df0afc4f0.tar.xz | |
Intel Common SOC: Add romstage support
Provide a common romstage implementation for the Intel SOCs.
BRANCH=none
BUG=None
TEST=Build for Braswell
Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/Makefile.inc')
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 6d40aa7037..76854ad857 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,10 +1,19 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c +romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c + +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c ramstage-y += hda_verb.c -ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c +ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c endif |