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| author | Werner Zeh <werner.zeh@siemens.com> | 2016-02-19 10:50:38 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2016-02-25 15:16:44 +0100 |
| commit | 1c3b1112fa2dbdd66b0470224715dc6da254ce62 (patch) | |
| tree | 3bdfc5078d9a098195ce604ccace6fa56af5a5f5 /src/soc/intel/fsp_baytrail/Makefile.inc | |
| parent | 01554574492a4965668e0d9423d3ae4da079cfde (diff) | |
| download | coreboot-1c3b1112fa2dbdd66b0470224715dc6da254ce62.tar.xz | |
fsp_baytrail: Fix a possible hanging DisplayPort
On some devices it can happen that DisplayPort TX lanes
do not work properly if the power gate setup is omitted.
If that happens, DisplayPort training will fail and therefore
DisplayPort channel will not work. Both ports are affected.
It seems that not every CPU shows this effect
and those that are affected tend to fail more often in a cold
environment.
With this fix a board that originally shows this failure
was running for over 1000 power cycles without issues.
Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13743
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/Makefile.inc')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 79fc7eb79c..41672e6abf 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -3,6 +3,7 @@ # # Copyright (C) 2010 Google Inc. # Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2016 Siemens AG # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -54,6 +55,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c +ramstage-(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp |