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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-18 15:26:48 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-27 08:26:16 +0000 |
| commit | f5cf60f25b8c77e0c90094e3326c5bc0e37cb383 (patch) | |
| tree | 63967d01ebab0c1cdb41c58d4c52fea1d45616a4 /src/soc/intel/fsp_baytrail | |
| parent | 12724d6ad6fd6ab0ca8ea5d258c0ca7cce807441 (diff) | |
| download | coreboot-f5cf60f25b8c77e0c90094e3326c5bc0e37cb383.tar.xz | |
Move calls to quick_ram_check() before CBMEM init
After raminit completes, do a read-modify-write test
just below CBMEM top address. If test fails, die().
Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/romstage/romstage.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index b4eb006aab..c46b09ef97 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -15,7 +15,6 @@ */ #include <stddef.h> -#include <lib.h> #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -245,12 +244,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) late_mainboard_romstage_entry(); post_code(0x4c); - /* if S3 resume skip RAM check */ - if (prev_sleep_state != ACPI_S3) { - quick_ram_check(); - post_code(0x4d); - } - cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ |