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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-02 14:31:02 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-04 22:36:53 +0200 |
| commit | 4dd34eee092276e47a9be41ff9a51dfcde38d759 (patch) | |
| tree | abdacd55254200959e82094f6f9c0bf962235661 /src/soc/intel/quark/Makefile.inc | |
| parent | 5c4ddebb1631165f9bd36f6ea629b39a290afff4 (diff) | |
| download | coreboot-4dd34eee092276e47a9be41ff9a51dfcde38d759.tar.xz | |
soc/intel/quark: Add USB PHY initialization
Add register access support using register scripts.
Initialize the USB PHY using register scripts.
TEST=Build and run on Galileo Gen2
Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14496
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/Makefile.inc')
| -rw-r--r-- | src/soc/intel/quark/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index d8650fa8b9..3a865b8697 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -19,6 +19,7 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c @@ -27,9 +28,11 @@ ramstage-y += chip.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += pmc.c +ramstage-y += reg_access.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c +ramstage-y += usb.c CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include |