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| author | Nico Huber <nico.h@gmx.de> | 2018-05-27 14:37:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 08:22:20 +0000 |
| commit | 6ea6775fa3eaa78b5322833940b9ba32d784556b (patch) | |
| tree | fed449179d0025ee3efcc697f1755b676fac3baa /src/soc/intel/quark | |
| parent | 089b9089c111da9175d87c4f2671ba8ebe353b4b (diff) | |
| download | coreboot-6ea6775fa3eaa78b5322833940b9ba32d784556b.tar.xz | |
soc/{amd,intel}: Use postcar_frame_add_romcache()
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark')
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 74796448c4..900ec1b4ca 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -80,8 +80,7 @@ asmlinkage void *car_stage_c_entry(void) postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); /* Cache SPI flash - Write protect not supported */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRTHROUGH); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); run_postcar_phase(&pcf); return NULL; |