diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-07-24 00:36:12 +0530 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-28 05:15:58 +0200 |
| commit | e4a8537ce20d801a5985ba6268ae83593063a4bf (patch) | |
| tree | efdc7dcf51a9b91f8d4f6f8db9c8a0ef951ca62d /src/soc/intel/skylake/Kconfig | |
| parent | 68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 (diff) | |
| download | coreboot-e4a8537ce20d801a5985ba6268ae83593063a4bf.tar.xz | |
soc/intel/skylake: Add C entry bootblock support
List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34
Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/Kconfig')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 5f12f5bb4a..bbffd17f6d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select ACPI_NHLT + select BOOTBLOCK_CONSOLE select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select C_ENVIRONMENT_BOOTBLOCK @@ -61,22 +62,10 @@ config CHROMEOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH select VIRTUAL_DEV_SWITCH -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/skylake/bootblock/cpu.c" - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "soc/intel/skylake/bootblock/systemagent.c" - config BOOTBLOCK_RESETS string default "soc/intel/common/reset.c" -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "soc/intel/skylake/bootblock/pch.c" - config CBFS_SIZE hex default 0x200000 |