diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-11-09 15:07:44 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-15 16:44:36 +0000 |
| commit | bffff54e09e3fb91f94bd126814aaf1c200fa96b (patch) | |
| tree | bcb679e890611bef95bfba85511b1db4b63ee052 /src/soc/intel/skylake/bootblock | |
| parent | 4a722f5e2f1e677f7bae3d5eb39048aa541b5cb6 (diff) | |
| download | coreboot-bffff54e09e3fb91f94bd126814aaf1c200fa96b.tar.xz | |
soc/intel/skylake: Make use of common CSE code for skylake
TEST=Ensures global reset could able to reset system.
Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/bootblock')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 25 |
1 files changed, 3 insertions, 22 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index fdc88f5641..34cfaa34e8 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -18,6 +18,7 @@ #include <chip.h> #include <device/device.h> #include <device/pci_def.h> +#include <intelblocks/cse.h> #include <intelblocks/fast_spi.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> @@ -157,27 +158,6 @@ static void soc_config_tco(void) outw(tcocnt, tcobase + TCO1_CNT); } -static void enable_heci(void) -{ - device_t dev = PCH_DEV_CSE; - u8 pcireg; - - /* Assign Resources to HECI1 */ - /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for HECI1 */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); -} - void pch_early_iorange_init(void) { /* IO Decode Range */ @@ -216,5 +196,6 @@ void pch_early_init(void) enable_rtc_upper_bank(); - enable_heci(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); } |