diff options
| author | Sooi, Li Cheng <li.cheng.sooi@intel.com> | 2017-01-04 13:36:06 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-02-16 05:09:13 +0100 |
| commit | c76e9982b231023ccf91b79ec7526e50f595ffc1 (patch) | |
| tree | 31ec30fe5f48efbc92a5e17385687892a0e20e9f /src/soc/intel/skylake/include | |
| parent | 901efea8abbb3131685fd69fd4ad7c5093c8cb3c (diff) | |
| download | coreboot-c76e9982b231023ccf91b79ec7526e50f595ffc1.tar.xz | |
soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC
Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC
Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7
Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com>
Reviewed-on: https://review.coreboot.org/18028
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/cpu.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pch.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/systemagent.h | 6 |
3 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index ecb9833277..35a30819b2 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -26,8 +26,12 @@ /* Supported CPUIDs */ #define CPUID_SKYLAKE_C0 0x406e2 #define CPUID_SKYLAKE_D0 0x406e3 +#define CPUID_SKYLAKE_HQ0 0x506e1 +#define CPUID_SKYLAKE_HR0 0x506e3 #define CPUID_KABYLAKE_G0 0x406e8 #define CPUID_KABYLAKE_H0 0x806e9 +#define CPUID_KABYLAKE_HA0 0x506e8 +#define CPUID_KABYLAKE_HB0 0x906e9 /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index 701a6f5edf..9be75bf98f 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -26,6 +26,9 @@ #define PCH_SPT_LP_U_BASE 0x9d43 #define PCH_SPT_LP_U_PREMIUM 0x9d48 #define PCH_SPT_LP_Y_PREMIUM 0x9d46 +#define PCH_SPT_H_C236 0xa150 +#define PCH_SPT_H_PREMIUM 0xa14e +#define PCH_SPT_H_QM170 0xa14d #define PCH_KBL_LP_Y_PREMIUM_HDCP22 0x9d4b #define PCH_KBL_LP_U_PREMIUM 0x9d58 #define PCH_KBL_LP_Y_PREMIUM 0x9d56 diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 6353ea627e..c82f6913b2 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -25,15 +25,21 @@ #define IGD_SKYLAKE_GT1_SULTM 0x1906 #define IGD_SKYLAKE_GT2_SULXM 0x191E #define IGD_SKYLAKE_GT2_SULTM 0x1916 +#define IGD_SKYLAKE_GT2_SHALM 0x191B +#define IGD_SKYLAKE_GT4_SHALM 0x193D #define IGD_KABYLAKE_GT1_SULTM 0x5906 #define IGD_KABYLAKE_GT2_SULXM 0x591E #define IGD_KABYLAKE_GT2_SULTM 0x5916 +#define IGD_KABYLAKE_GT2_SHALM 0x591B #define MCH_SKYLAKE_ID_U 0x1904 #define MCH_SKYLAKE_ID_Y 0x190c #define MCH_SKYLAKE_ID_ULX 0x1924 +#define MCH_SKYLAKE_ID_H 0x1910 +#define MCH_SKYLAKE_ID_H_EM 0x1918 #define MCH_KABYLAKE_ID_U 0x5904 #define MCH_KABYLAKE_ID_Y 0x590c +#define MCH_KABYLAKE_ID_H 0x5910 /* Device 0:0.0 PCI configuration space */ |