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| author | Nico Huber <nico.h@gmx.de> | 2019-05-04 16:59:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 15:55:50 +0000 |
| commit | 66318aad07e6810065bc0668f4a1f34b7cb77687 (patch) | |
| tree | 6b55edcdc8f54bf0d0f65365cd7ee0ccb5fe2884 /src/soc/intel/skylake/romstage/romstage.c | |
| parent | 99e836c843e6a8536348d5cc9581b5a17512a263 (diff) | |
| download | coreboot-66318aad07e6810065bc0668f4a1f34b7cb77687.tar.xz | |
intel/fsp1_1: Move MRC cache pointers into `romstage_params`
These are part of a common concept and not SoC specific.
Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 0501b04493..8ec08c2d0f 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -46,6 +46,12 @@ void soc_pre_ram_init(struct romstage_params *params) /* Prepare to initialize memory */ soc_fill_pei_data(params->pei_data); + + const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *const config = + dev ? dev->chip_info : NULL; + /* Force a full memory train if RMT is enabled */ + params->disable_saved_data = config && config->Rmt; } /* UPD parameters to be initialized before MemoryInit */ |