diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-12-21 10:58:26 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-12-23 04:54:35 +0100 |
| commit | 42cfdf5184b3e94805958a3368f2e049c09119ac (patch) | |
| tree | ed67de96fd6e25054aca74916acd5e36282c4388 /src/soc/intel/skylake/romstage | |
| parent | 45e11aa0a573aba1e4d8ae8dcd2cc87a8ca87dab (diff) | |
| download | coreboot-42cfdf5184b3e94805958a3368f2e049c09119ac.tar.xz | |
soc/intel/skylake: Use the new SPI driver interface
1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash
controller in different files.
BUG=chrome-os-partner:59832
BRANCh=None
TEST=Compiles successfully for chell and eve.
Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c index 16224046d7..41e06a7933 100644 --- a/src/soc/intel/skylake/romstage/spi.c +++ b/src/soc/intel/skylake/romstage/spi.c @@ -27,7 +27,7 @@ int early_spi_read_wpsr(u8 *sr) uint8_t rdsr; int ret = 0; - spi_init(); + spi_flash_init(); /* sending NULL for spiflash struct parameter since we are not * calling HWSEQ read_status() call via Probe. |