soc/intel/tigerlake: Update C-State info

C-State latency table was exposed by both intel-idle driver and
BIOS/coreboot. And table in Kernel was used before.
After kernel patch (https://patchwork.kernel.org/patch/11290319/),
only BIOS/coreboot exposes C-State latency table through _CST.
As current C-State latency table info is not correct for Tigerlake,
update proper info according to BWG and reference code.

- Update latency: CpuPowerMgmt.h
  Use BIOS reference code as values in BWG is not up-to-dated
- Remove MSR program for latency: BWG 4.6.4.3.4

Reference:
- TGL BWG #611569 Rev 0.7.6
- https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/
ClientOneSiliconPkg/Cpu/Include/CpuPowerMgmt.h

BUG=b:155223704
BRANCH=None
TEST=Boot to OS and check C-State latency
expected result
>cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}
POLL
C1_ACPI
C2_ACPI
C3_ACPI
0
1
253
1048

For detail, refer Bug info.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8bf2976ad35b4cf6f637a99c26b4f98f9f6ee563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>

1 files changed, 13 insertions, 13 deletions

diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 58c8e9ccf1..ac296ed945 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -53,70 +53,70 @@ enum {
 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
 	[C_STATE_C0] = {},
 	[C_STATE_C1] = {
-		.latency = 0,
+		.latency = C1_LATENCY,
 		.power = C1_POWER,
 		.resource = MWAIT_RES(0, 0),
 	},
 	[C_STATE_C1E] = {
-		.latency = 0,
+		.latency = C1_LATENCY,
 		.power = C1_POWER,
 		.resource = MWAIT_RES(0, 1),
 	},
 	[C_STATE_C6_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C6_LATENCY,
 		.power = C6_POWER,
 		.resource = MWAIT_RES(2, 0),
 	},
 	[C_STATE_C6_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C6_LATENCY,
 		.power = C6_POWER,
 		.resource = MWAIT_RES(2, 1),
 	},
 	[C_STATE_C7_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C7_LATENCY,
 		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 0),
 	},
 	[C_STATE_C7_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C7_LATENCY,
 		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 1),
 	},
 	[C_STATE_C7S_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C7_LATENCY,
 		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 2),
 	},
 	[C_STATE_C7S_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C7_LATENCY,
 		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 3),
 	},
 	[C_STATE_C8] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C8_LATENCY,
 		.power = C8_POWER,
 		.resource = MWAIT_RES(4, 0),
 	},
 	[C_STATE_C9] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C9_LATENCY,
 		.power = C9_POWER,
 		.resource = MWAIT_RES(5, 0),
 	},
 	[C_STATE_C10] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.latency = C10_LATENCY,
 		.power = C10_POWER,
 		.resource = MWAIT_RES(6, 0),
 	},
 };
 
 static int cstate_set_non_s0ix[] = {
-	C_STATE_C1E,
+	C_STATE_C1,
 	C_STATE_C6_LONG_LAT,
 	C_STATE_C7S_LONG_LAT
 };
 
 static int cstate_set_s0ix[] = {
-	C_STATE_C1E,
+	C_STATE_C1,
 	C_STATE_C7S_LONG_LAT,
 	C_STATE_C10
 };