coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-11	soc/intel/tigerlake: Update C-State info	Wonkyu Kim
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-04-28	device: Constify struct device * parameter to write_acpi_tables	Furquan Shaikh
2020-04-24	soc/intel/tigerlake: Add ACPI GPIO op	Alex Levin
2020-04-14	soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type	John Zhao
2020-04-13	acpi: Bump FADT to revision 6	Patrick Rudolph
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-12	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	John Zhao
2020-01-10	soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper	Subrata Banik
2019-12-31	soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT	Meera Ravindranath
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik