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authorMeera Ravindranath <meera.ravindranath@intel.com>2020-04-29 12:19:33 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:27:32 +0000
commit0d6cc2201713fef102d7229f24e97428679aec68 (patch)
tree44ba6073adaf450c880c4606e047e2ecee587313 /src/soc/intel/tigerlake/chip.h
parent4c7bc8db749ffaf0bb3a54b43b0a56652285cde9 (diff)
downloadcoreboot-0d6cc2201713fef102d7229f24e97428679aec68.tar.xz
soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
-rw-r--r--src/soc/intel/tigerlake/chip.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index a3319d4ee4..fe338352fb 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -107,6 +107,9 @@ struct soc_intel_tigerlake_config {
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
+ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,