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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-09 06:37:24 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-10 09:54:55 +0000
commit6390c5070363d834443ecdfb6b77c077fc2576dd (patch)
treef93e70502164140a54e43389fe0246107e913dc6 /src/soc/intel
parentf5a57a883b6586c0e6dce9e6e34add09a96e647e (diff)
downloadcoreboot-6390c5070363d834443ecdfb6b77c077fc2576dd.tar.xz
soc/intel/denverton_ns: Fix missing tsc_freq_mhz()
It was relying on bad weak implementation for postcar and verstage. Change-Id: I5a520e0166198c0565349c164f143f4a43649861 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Guckian Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/denverton_ns/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc
index c024c3af67..e9d5022511 100644
--- a/src/soc/intel/denverton_ns/Makefile.inc
+++ b/src/soc/intel/denverton_ns/Makefile.inc
@@ -31,6 +31,7 @@ bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
postcar-y += memmap.c
postcar-y += spi.c
+postcar-y += tsc_freq.c
postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
romstage-y += memmap.c
@@ -80,6 +81,7 @@ smm-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
verstage-y += memmap.c
verstage-y += reset.c
verstage-y += spi.c
+verstage-y += tsc_freq.c
verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include