summaryrefslogtreecommitdiff
path: root/src/soc/nvidia/tegra132/clock.c
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@google.com>2014-08-09 01:55:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-03-26 00:26:52 +0100
commitc41dfb0626eb06616c5d632f7f72c9af29fad331 (patch)
treeaf7d6c9dd7bde89b1163dbe14401afe97ca73dbf /src/soc/nvidia/tegra132/clock.c
parent6d7c9acc179a072fd2c19516339f90751402bc74 (diff)
downloadcoreboot-c41dfb0626eb06616c5d632f7f72c9af29fad331.tar.xz
t132: Implement clock initialization api for functional units
This api provides a common interface to initialize various clock sources, dividers as well as enabling the clock for various functional units. BUG=chrome-os-partner:31251 BRANCH=None TEST=Compiles successfully for rush and boots till last known good point. Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3 Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211765 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/clock.c')
-rw-r--r--src/soc/nvidia/tegra132/clock.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index fb8e85feee..ed5afbaa45 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -576,6 +576,14 @@ void clock_init(void)
graphics_pll();
}
+void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg,
+ u32 *rst_dev_clr_reg)
+{
+ writel(val, clk_enb_set_reg);
+ udelay(IO_STABILIZATION_DELAY);
+ writel(val, rst_dev_clr_reg);
+}
+
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
{
if (l)