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| author | Xiang Wang <wxjstz@126.com> | 2018-08-28 16:34:29 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-10 15:03:08 +0000 |
| commit | 2e38dbe5f1a9db76cdf529679faee63fcb6a9c34 (patch) | |
| tree | 3656f083f5aad2fc009d1038c313b8cfd695895f /src/soc/ucb/riscv/Makefile.inc | |
| parent | 0370bcf40ce3a07e6e2d33b8bcebf28a0ac98807 (diff) | |
| download | coreboot-2e38dbe5f1a9db76cdf529679faee63fcb6a9c34.tar.xz | |
riscv: update mtime initialization
Add a interface, which is implemented by SoC.
Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/soc/ucb/riscv/Makefile.inc')
| -rw-r--r-- | src/soc/ucb/riscv/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index 1072a2b32e..16225c0968 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y) +bootblock-y += mtime.c romstage-y += cbmem.c ramstage-y += cbmem.c |