diff options
| author | Sourabh Banerjee <sbanerje@codeaurora.org> | 2015-04-24 22:54:18 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-02 11:40:34 +0200 |
| commit | 0bd22ce82c6e4beaacfe591a6ae8ce2874d042b7 (patch) | |
| tree | a430ac8831e0b24b10ee66eeee2beaae557f8aee /src/soc | |
| parent | 641529b0678d7399c9072f23891151ecfb13ae27 (diff) | |
| download | coreboot-0bd22ce82c6e4beaacfe591a6ae8ce2874d042b7.tar.xz | |
ipq806x: clear the RPM initialization Acknowledge bit
The RPM initialization Acknowledge is cleared by writing 1
into bit-10 of the RPM_INT_ACK register.
The existing code got it wrong and is writing zero to that bit.
BRANCH=storm
BUG=chrome-os-partner:39231
TEST=with this patch and an RPM firmware update, an SP4 device
survived more than 1000 reboots in a row.
Change-Id: Ibba296ed0571ad9403a0c51c7f82f07f185b4e83
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 13b4a0f093ba652ad6bccdfc4b3686c0741c6fe7
Original-Change-Id: I39e6ea50e0f66b4af68bdb868dd4437c34bb4524
Original-Signed-off-by: Viswanath Kraleti <vkraleti@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/266969
Original-Reviewed-by: Manoj Juneja <mjuneja@qti.qualcomm.com>
Reviewed-on: http://review.coreboot.org/10310
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/blobs_init.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index dc522003ba..ae7e4d4b48 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -131,7 +131,11 @@ void start_rpm(void) printk(BIOS_INFO, "Starting RPM\n"); /* Clear 'ready' indication. */ - write32(RPM_INT_ACK, read32(RPM_INT_ACK) & ~ready_mask); + /* + * RPM_INT_ACK is clear-on-write type register, + * read-modify-write is not recommended. + */ + write32(RPM_INT_ACK, ready_mask); /* Set RPM entry address */ write32(RPM_SIGNAL_ENTRY, load_addr); |