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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-04 10:56:28 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-05 20:09:41 +0000 |
| commit | 0c057c21e57e01a223d6f38c83d5e75a8e23b2ab (patch) | |
| tree | 51a41024cb8f874de8618e8cc2c86a66c338d0e4 /src/soc | |
| parent | e94a578039a698c7ffb7e2ba1ff64e9a9ea9dbf1 (diff) | |
| download | coreboot-0c057c21e57e01a223d6f38c83d5e75a8e23b2ab.tar.xz | |
soc/intel/adl, mb/google/brya: Add IPU to devicetree
BUG=b:181843816
Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 5e63007c0f..f22d1d4b87 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -57,6 +57,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 173d3e037f..cd9ebf9192 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -5,6 +5,7 @@ chip soc/intel/alderlake device pci 01.0 alias pcie5 off end device pci 02.0 alias igpu off end device pci 04.0 alias dtt off end + device pci 05.0 alias ipu off end device pci 06.0 alias pcie4_0 off end device pci 06.2 alias pcie4_1 off end device pci 07.0 alias tbt_pcie_rp0 off |