diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 14:18:40 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 08:47:06 +0000 |
| commit | 11fdb17564bd4d3e3539c9855be88dd7e5fd8061 (patch) | |
| tree | 98f25191b0d10d7436b56e4d8b926fa40a098ab4 /src/soc | |
| parent | 3fa23b8c008709e4204992c52fcd5b729454b333 (diff) | |
| download | coreboot-11fdb17564bd4d3e3539c9855be88dd7e5fd8061.tar.xz | |
soc/intel/broadwell/pch/sata.c: Don't enable Bus Master
Bus Master is not required and reference code does not set it.
Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/pch/sata.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index b496e53e3d..82760aba86 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -35,9 +35,8 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ |