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authorRex-BC Chen <rex-bc.chen@mediatek.com>2021-05-13 15:34:02 +0800
committerHung-Te Lin <hungte@chromium.org>2021-05-14 04:00:16 +0000
commit156210a7184940a4ad6db81c37476e0ee53299ff (patch)
tree345b3ed6d52615887436c74535760976c4a221b2 /src/soc
parent8a5441d5fb1ec8b73ffa28501170d968f7e37b2f (diff)
downloadcoreboot-156210a7184940a4ad6db81c37476e0ee53299ff.tar.xz
soc/mediatek/mt8195: Initialize DRAM in romstage
Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/mediatek/mt8195/Kconfig1
-rw-r--r--src/soc/mediatek/mt8195/Makefile.inc15
-rw-r--r--src/soc/mediatek/mt8195/include/soc/dramc_soc.h50
-rw-r--r--src/soc/mediatek/mt8195/include/soc/emi.h10
4 files changed, 66 insertions, 10 deletions
diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig
index bed3e04250..203e9251a0 100644
--- a/src/soc/mediatek/mt8195/Kconfig
+++ b/src/soc/mediatek/mt8195/Kconfig
@@ -5,6 +5,7 @@ config SOC_MEDIATEK_MT8195
select ARCH_VERSTAGE_ARMV8_64
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_RAMSTAGE_ARMV8_64
+ select CACHE_MRC_SETTINGS
select HAVE_UART_SPECIAL
select SOC_MEDIATEK_COMMON
select CLEAR_WDT_MODE_REG
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index a04ccf4a19..7cbfa8e7db 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -22,10 +22,14 @@ verstage-y += ../common/wdt.c
romstage-y += ../common/cbmem.c
romstage-y += ../common/clkbuf.c
+romstage-y += ../common/dram_init.c
+romstage-y += ../common/dramc_param.c
romstage-y += emi.c
romstage-y += ../common/flash_controller.c
romstage-y += ../common/gpio.c gpio.c
romstage-y += ../common/i2c.c i2c.c
+romstage-y += ../common/memory.c
+romstage-y += ../common/memory_test.c
romstage-y += ../common/mmu_operations.c mmu_operations.c
romstage-y += ../common/pll.c pll.c
romstage-y += scp.c
@@ -55,8 +59,19 @@ ramstage-y += ../common/usb.c usb.c
ramstage-y += ../common/wdt.c
ramstage-y += mt6360.c
+MT8195_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8195
+
+DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
+$(DRAM_CBFS)-file := $(MT8195_BLOB_DIR)/dram.elf
+$(DRAM_CBFS)-type := stage
+$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
+ifneq ($(wildcard $($(DRAM_CBFS)-file)),)
+ cbfs-files-y += $(DRAM_CBFS)
+endif
+
CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8195/include
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_soc.h b/src/soc/mediatek/mt8195/include/soc/dramc_soc.h
new file mode 100644
index 0000000000..6040297992
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/dramc_soc.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__
+#define __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__
+
+typedef enum {
+ CHANNEL_A = 0,
+ CHANNEL_B,
+ CHANNEL_C,
+ CHANNEL_D,
+ CHANNEL_MAX,
+} DRAM_CHANNEL_T;
+
+typedef enum {
+ RANK_0 = 0,
+ RANK_1,
+ RANK_MAX,
+} DRAM_RANK_T;
+
+/* DRAM SHUFFLE register type */
+typedef enum {
+ DRAM_DFS_SHUFFLE_1 = 0,
+ DRAM_DFS_SHUFFLE_2,
+ DRAM_DFS_SHUFFLE_3,
+ DRAM_DFS_SHUFFLE_4,
+ DRAM_DFS_SHUFFLE_5,
+ DRAM_DFS_SHUFFLE_6,
+ DRAM_DFS_SHUFFLE_7,
+ DRAM_DFS_SHUFFLE_MAX,
+} DRAM_DFS_SHUFFLE_TYPE_T;
+
+/*
+ * Internal CBT mode enum
+ * 1. Calibration flow uses vGet_Dram_CBT_Mode to
+ * differentiate between mixed vs non-mixed LP4
+ * 2. Declared as dram_cbt_mode[RANK_MAX] internally to
+ * store each rank's CBT mode type
+ */
+typedef enum {
+ CBT_NORMAL_MODE = 0,
+ CBT_BYTE_MODE1,
+} DRAM_CBT_MODE_T;
+
+#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX
+
+#define DQS_NUMBER_LP4 2
+#define DQS_BIT_NUMBER 8
+#define DQ_DATA_WIDTH_LP4 16
+
+#endif /* __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__ */
diff --git a/src/soc/mediatek/mt8195/include/soc/emi.h b/src/soc/mediatek/mt8195/include/soc/emi.h
deleted file mode 100644
index 33ff1bf0af..0000000000
--- a/src/soc/mediatek/mt8195/include/soc/emi.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_MEDIATEK_MT8195_EMI_H
-#define SOC_MEDIATEK_MT8195_EMI_H
-
-#include <stddef.h>
-
-size_t sdram_size(void);
-
-#endif /* SOC_MEDIATEK_MT8195_EMI_H */