soc/intel/common: pmclib: make use of the new ETR address API

Make use of the new ETR address API in the ETR3 register related
functions.

Further, disabling and locking of global reset is now done at once to
save one read-modify-write cycle, thus the function was renamed
accordingly and the now redundant disabling in soc/apl got removed.

Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

3 files changed, 17 insertions, 27 deletions

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1aab8a1b7a..6c195bb6fd 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -418,10 +418,8 @@ static void soc_init(void *data)
 
 static void soc_final(void *data)
 {
-	/* Disable global reset, just in case */
-	pmc_global_reset_enable(0);
 	/* Make sure payload/OS can't trigger global reset */
-	pmc_global_reset_lock();
+	pmc_global_reset_disable_and_lock();
 }
 
 static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index 7cc501df7e..b622a74b9b 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -133,10 +133,15 @@ void pmc_clear_prsts(void);
  */
 void pmc_global_reset_enable(bool enable);
 /*
- * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
- * This lock is reset on cold boot, hard reset, soft reset and Sx.
+ * Disable global reset and lock the CF9 global reset register in accordance to PCH ME BWG
+ * sections 4.4.1, 4.5.1 and 18.4 and the PCH datasheet(s) (Intel doc e.g. 332691-002EN,
+ * 332996-002EN). Deviate from the BGW we don't depend on the Intel ME state because Intel
+ * FPT (Flash Programming Tool) normally is not used with coreboot.
+ *
+ * Once the register is locked, it can't be changed. This lock is reset on cold boot, hard
+ * reset, soft reset and Sx.
  */
-void pmc_global_reset_lock(void);
+void pmc_global_reset_disable_and_lock(void);
 
 /* Returns the power state structure */
 struct chipset_power_state *pmc_get_power_state(void);
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index d7362b6dc4..82b391b958 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -420,37 +420,24 @@ int pmc_fill_power_state(struct chipset_power_state *ps)
 }
 
 #if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK)
-/*
- * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
- * This lock is reset on cold boot, hard reset, soft reset and Sx.
- */
-void pmc_global_reset_lock(void)
+void pmc_global_reset_disable_and_lock(void)
 {
-	/* Read PMC base address from soc */
-	uintptr_t etr = soc_read_pmc_base() + ETR;
+	uint32_t *etr = soc_pmc_etr_addr();
 	uint32_t reg;
 
-	reg = read32((void *)etr);
-	if (reg & CF9_LOCK)
-		return;
-	reg |= CF9_LOCK;
-	write32((void *)etr, reg);
+	reg = read32(etr);
+	reg = (reg & ~CF9_GLB_RST) | CF9_LOCK;
+	write32(etr, reg);
 }
 
-/*
- * Enable or disable global reset. If global reset is enabled, hard reset and
- * soft reset will trigger global reset, where both host and TXE are reset.
- * This is cleared on cold boot, hard reset, soft reset and Sx.
- */
 void pmc_global_reset_enable(bool enable)
 {
-	/* Read PMC base address from soc */
-	uintptr_t etr = soc_read_pmc_base() + ETR;
+	uint32_t *etr = soc_pmc_etr_addr();
 	uint32_t reg;
 
-	reg = read32((void *)etr);
+	reg = read32(etr);
 	reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
-	write32((void *)etr, reg);
+	write32(etr, reg);
 }
 #endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK