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| author | Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> | 2020-09-02 17:51:09 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-09-11 15:32:14 +0000 |
| commit | 1e633e88dd69a13361c2d256ce7c5e63e84415b6 (patch) | |
| tree | 30d7ef4879690ae8b7caa7a4ef6ce66ca1061fc6 /src/soc | |
| parent | 1fa45b1460d9922a38fd995b8d48bf84fc5c7975 (diff) | |
| download | coreboot-1e633e88dd69a13361c2d256ce7c5e63e84415b6.tar.xz | |
soc/amd/picasso: Fix TSC frequency calculation
Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.
BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork
Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/tsc_freq.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index a86080cb4c..8a541fc4a2 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -7,6 +7,10 @@ static unsigned long mhz; +/* Use this default TSC frequency when it can not be correctly calculated. + Higher numbers are safer as it will result in longer delays using TSC */ +#define TSC_DEFAULT_FREQ_MHZ 4000 + unsigned long tsc_freq_mhz(void) { msr_t msr; @@ -22,9 +26,19 @@ unsigned long tsc_freq_mhz(void) if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); - cpufid = (msr.lo & 0x3f); - cpudid = (msr.lo & 0x1c0) >> 6; + cpufid = (msr.lo & 0xff); + cpudid = (msr.lo & 0x3f00) >> 8; + + /* normally core frequency is calculated as (fid * 25) / (did / 8) */ + if (!cpudid) { + mhz = TSC_DEFAULT_FREQ_MHZ; + printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz); + } else if ((cpudid >= 8) && (cpudid < 0x3c)) { + mhz = (200 * cpufid) / cpudid; + } else { + mhz = 25 * cpufid; + printk(BIOS_ERR, "Invalid frequency divisor 0x%x, assume 1\n", cpudid); + } - mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid); return mhz; } |