diff options
| author | David Imhoff <dimhoff_devel@xs4all.nl> | 2015-05-10 15:15:25 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-16 18:22:20 +0100 |
| commit | 24f5164a261f31959fa44344b60024726fb1f597 (patch) | |
| tree | 569c92d6db0babf1dd25e394303df7053a42d8c2 /src/soc | |
| parent | b7d44dfcf59a6d09194f73dd37b79539be0c797a (diff) | |
| download | coreboot-24f5164a261f31959fa44344b60024726fb1f597.tar.xz | |
intel/fsp_baytrail: Always log PcdEnableLpe and PcdeMMCBootMode
Log the values of PcdEnableLpe and PcdeMMCBootMode even if they are
outside of the expected range.
TEST=Intel/MinnowMax
Change-Id: Ie0aea4287234b23d4e9852f3991dcc78ce8103d9
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: https://review.coreboot.org/10164
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index fb179e65dc..640331bf41 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -209,10 +209,17 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U if (UpdData->PcdEnableLpe < sizeof(acpi_pci_mode_strings) / sizeof (char *)) printk(FSP_INFO_LEVEL, "Lpe:\t\t\t%s\n", acpi_pci_mode_strings[UpdData->PcdEnableLpe]); + else + printk(FSP_INFO_LEVEL, "Lpe:\t\t\tUnknown (0x%02x)\n", + UpdData->PcdEnableLpe); if (UpdData->PcdeMMCBootMode < sizeof(emmc_mode_strings) / sizeof (char *)) printk(FSP_INFO_LEVEL, "eMMC Mode:\t\t%s\n", emmc_mode_strings[UpdData->PcdeMMCBootMode]); + else + printk(FSP_INFO_LEVEL, "eMMC Mode:\t\tUnknown (0x%02x)\n", + UpdData->PcdeMMCBootMode); + if (UpdData->PcdEnableSata) printk(FSP_INFO_LEVEL, "SATA Mode:\t\t%s\n", |