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| author | Yu-Ping Wu <yupingso@google.com> | 2020-10-21 18:23:03 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-22 14:25:46 +0000 |
| commit | 37765930ecebb0caf3abc71ffbf192f5e7cdfc8d (patch) | |
| tree | 6cee6d28f0eae1c7d51be10e4a416dc921ccfd64 /src/soc | |
| parent | 279c3e1e7d888af378e85f51bbfa3bbe667909b1 (diff) | |
| download | coreboot-37765930ecebb0caf3abc71ffbf192f5e7cdfc8d.tar.xz | |
soc/mediatek/mt8183: Fix pq module size config
For pq module size registers such as DISP_AAL_SIZE, the high bits
should be HSIZE, while low bits should be VSIZE. Fix the incorrect
settings for these registers where width and height are reversed.
According to MediaTek, there is no practical impact on mt8183 devices,
but it's still nice to get this fixed to avoid future confusion.
BUG=b:171167210
TEST=none
BRANCH=kukui
Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46626
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8183/ddp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index eba3f5e348..395c8212a1 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -34,7 +34,7 @@ static void ovl_bgclr_in_sel(u32 idx) static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, int enable_relay) { - write32(®s->size, height << 16 | width); + write32(®s->size, width << 16 | height); if (enable_relay) write32(®s->cfg, PQ_RELAY_MODE); write32(®s->en, PQ_EN); |