nyan*: enable CLAMP_INPUTS

Enable pinmux clamp function to avoid pinmux conflict.
For pins which are configured to tristate enabled, the inputs to the
controller will be clamped to zero. This can be used to avoid pinmux
conflicts since the tristate bit is set to 1 in the power-on-reset
pinmux setting.
With pinmux clamp enabled, we need to configure all the input pins
to tristate disabled.
BUG=chrome-os-partner:27091
BRANCH=None
TEST=built and booted successfully, display worked fine.

Original-Change-Id: Id79a717f2025c812908c7152d439351208aee8d2
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194060
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit c95d6fe79810612cfad721667657cdcb87068d23)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1b23df8b90f83ea2b2c08c4364d90fe71533a5a0
Reviewed-on: http://review.coreboot.org/7775
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

4 files changed, 17 insertions, 5 deletions

diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c
index fea10b5dbe..5983d546d2 100644
--- a/src/soc/nvidia/tegra/apbmisc.c
+++ b/src/soc/nvidia/tegra/apbmisc.c
@@ -22,8 +22,14 @@
 
 #include "apbmisc.h"
 
+static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;
+
 void enable_jtag(void)
 {
-	struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;
 	write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
 }
+
+void clamp_tristate_inputs(void)
+{
+	write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
+}
diff --git a/src/soc/nvidia/tegra/apbmisc.h b/src/soc/nvidia/tegra/apbmisc.h
index 805d0bf18b..2f1811a1dd 100644
--- a/src/soc/nvidia/tegra/apbmisc.h
+++ b/src/soc/nvidia/tegra/apbmisc.h
@@ -25,11 +25,17 @@
 struct apbmisc {
 	u32 reserved0[9];		/* ABP_MISC_PP_ offsets 00-20 */
 	u32 pp_config_ctl;		/* _CONFIG_CTL_0, offset 24 */
+	u32 reserved1[6];		/* APB_MISC_PP_ offsets 28-3C */
+	u32 pp_pinmux_global;		/* _PINMUX_GLOBAL_0, offset 40 */
 };
 
 #define PP_CONFIG_CTL_TBE		(1 << 7)
 #define PP_CONFIG_CTL_JTAG		(1 << 6)
 
+#define PP_PINMUX_CLAMP_INPUTS		(1 << 0)
+
+
 void enable_jtag(void);
+void clamp_tristate_inputs(void);
 
 #endif	/* __SOC_NVIDIA_TEGRA_APBMISC_H__ */
diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c
index ac0fc3f986..b10cded12d 100644
--- a/src/soc/nvidia/tegra/gpio.c
+++ b/src/soc/nvidia/tegra/gpio.c
@@ -29,7 +29,7 @@
 
 void __gpio_input(gpio_t gpio, u32 pull)
 {
-	u32 pinmux_config = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | pull;
+	u32 pinmux_config = PINMUX_INPUT_ENABLE | pull;
 
 	gpio_set_int_enable(gpio, 0);
 	gpio_set_out_enable(gpio, 0);
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index 6acd5ad4d6..2857a90ace 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -31,6 +31,9 @@ void main(void)
 {
 	void *entry;
 
+	// enable pinmux clamp inputs
+	clamp_tristate_inputs();
+
 	// enable JTAG at the earliest stage
 	enable_jtag();
 
@@ -40,13 +43,11 @@ void main(void)
 	pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3);
 	// Serial in, tristate_on.
 	pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 |
-						 PINMUX_TRISTATE |
 						 PINMUX_PULL_UP |
 						 PINMUX_INPUT_ENABLE);
 	// Mux some pins away from uart A.
 	pinmux_set_config(PINMUX_UART2_CTS_N_INDEX,
 			  PINMUX_UART2_CTS_N_FUNC_UB3 |
-			  PINMUX_TRISTATE |
 			  PINMUX_INPUT_ENABLE);
 	pinmux_set_config(PINMUX_UART2_RTS_N_INDEX,
 			  PINMUX_UART2_RTS_N_FUNC_UB3);
@@ -66,7 +67,6 @@ void main(void)
 			  PINMUX_CPU_PWR_REQ_FUNC_CPU);
 	pinmux_set_config(PINMUX_PWR_INT_N_INDEX,
 			  PINMUX_PWR_INT_N_FUNC_PMICINTR |
-			  PINMUX_TRISTATE |
 			  PINMUX_INPUT_ENABLE);
 
 	power_enable_cpu_rail();