soc/intel: drop unneeded ISST configuration code

The code configuring ISST (Intel SpeedShift Technology) sets the ISST
capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware
P-States), which shall be done by the OS only.

Since the capability is enabled by default (opt-out), there is nothing
to do for us in the enabled-case. Practically speaking, there is no
value at all in disabling the capability, since one can configure the
OS to not enable HWP if that is desired.

The two other bits for EPP and HWP interrupt that were set by the code
are not set anymore, too. It was tested, on three platforms so far
(CML-U, KBL-H, SKL-U), that these are set as well by default in the
MSRs reset value (0x1cc0).

To reduce complexity and duplicated code without actual benefit, this
code gets dropped. The remaining dt option will be dropped in CB:46462.

Test: Linux on Supermicro X11SSM-F detects and enables HWP:
[    0.415017] intel_pstate: HWP enabled

Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 0 insertions, 196 deletions

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 9b7cc3e4dd..39a42651bd 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -31,31 +31,6 @@ static void soc_fsp_load(void)
 	fsps_load(romstage_handoff_is_resume());
 }
 
-static void configure_isst(void)
-{
-	config_t *conf = config_of_soc();
-	msr_t msr;
-
-	if (conf->speed_shift_enable) {
-		/*
-		 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		 * is supported or not. coreboot needs to configure MSR 0x1AA
-		 * which is then reflected in the CPUID register.
-		 */
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	} else {
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	}
-}
-
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -122,9 +97,6 @@ void soc_core_init(struct device *cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
-	/* Configure Intel Speed Shift */
-	configure_isst();
-
 	/* Enable PM timer emulation */
 	enable_pm_timer_emulation();
 
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index b6b921a29b..20da942f84 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -27,31 +27,6 @@ static void soc_fsp_load(void)
 	fsps_load(romstage_handoff_is_resume());
 }
 
-static void configure_isst(void)
-{
-	config_t *conf = config_of_soc();
-	msr_t msr;
-
-	if (conf->speed_shift_enable) {
-		/*
-		 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		 * is supported or not. coreboot needs to configure MSR 0x1AA
-		 * which is then reflected in the CPUID register.
-		 */
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	} else {
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	}
-}
-
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -158,9 +133,6 @@ void soc_core_init(struct device *cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
-	/* Configure Intel Speed Shift */
-	configure_isst();
-
 	set_aesni_lock();
 
 	/* Enable ACPI Timer Emulation via MSR 0x121 */
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index c51f3fa550..720a295e15 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -25,31 +25,6 @@ static void soc_fsp_load(void)
 	fsps_load(romstage_handoff_is_resume());
 }
 
-static void configure_isst(void)
-{
-	config_t *conf = config_of_soc();
-	msr_t msr;
-
-	if (conf->speed_shift_enable) {
-		/*
-		 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		 * is supported or not. coreboot needs to configure MSR 0x1AA
-		 * which is then reflected in the CPUID register.
-		 */
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	} else {
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	}
-}
-
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -116,9 +91,6 @@ void soc_core_init(struct device *cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
-	/* Configure Intel Speed Shift */
-	configure_isst();
-
 	/* Enable PM timer emulation */
 	enable_pm_timer_emulation();
 
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index b739d74db6..ea2b3574b2 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -25,31 +25,6 @@ static void soc_fsp_load(void)
 	fsps_load(romstage_handoff_is_resume());
 }
 
-static void configure_isst(void)
-{
-	config_t *conf = config_of_soc();
-	msr_t msr;
-
-	if (conf->speed_shift_enable) {
-		/*
-		 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		 * is supported or not. coreboot needs to configure MSR 0x1AA
-		 * which is then reflected in the CPUID register.
-		 */
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	} else {
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	}
-}
-
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -152,9 +127,6 @@ void soc_core_init(struct device *cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
-	/* Configure Intel Speed Shift */
-	configure_isst();
-
 	/* Enable PM timer emulation */
 	enable_pm_timer_emulation();
 
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 6f071c33f9..312fc7d7af 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -25,31 +25,6 @@ static void soc_fsp_load(void)
 	fsps_load(romstage_handoff_is_resume());
 }
 
-static void configure_isst(void)
-{
-	config_t *conf = config_of_soc();
-	msr_t msr;
-
-	if (conf->speed_shift_enable) {
-		/*
-		 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		 * is supported or not. coreboot needs to configure MSR 0x1AA
-		 * which is then reflected in the CPUID register.
-		 */
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	} else {
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	}
-}
-
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -116,9 +91,6 @@ void soc_core_init(struct device *cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
-	/* Configure Intel Speed Shift */
-	configure_isst();
-
 	/* Enable PM timer emulation */
 	enable_pm_timer_emulation();
 
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index fcec0cefba..1682503d4b 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -27,31 +27,6 @@
 
 #include "chip.h"
 
-static void configure_isst(void)
-{
-	config_t *conf = config_of_soc();
-	msr_t msr;
-
-	if (conf->speed_shift_enable) {
-		/*
-		 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		 * is supported or not. coreboot needs to configure MSR 0x1AA
-		 * which is then reflected in the CPUID register.
-		 */
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	} else {
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	}
-}
-
 static void configure_misc(void)
 {
 	config_t *conf = config_of_soc();
@@ -163,9 +138,6 @@ void soc_core_init(struct device *cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
-	/* Configure Intel Speed Shift */
-	configure_isst();
-
 	set_aesni_lock();
 
 	/* Enable ACPI Timer Emulation via MSR 0x121 */
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index e13712d05f..d7234e7191 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -31,31 +31,6 @@ static void soc_fsp_load(void)
 	fsps_load(romstage_handoff_is_resume());
 }
 
-static void configure_isst(void)
-{
-	config_t *conf = config_of_soc();
-	msr_t msr;
-
-	if (conf->speed_shift_enable) {
-		/*
-		 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		 * is supported or not. coreboot needs to configure MSR 0x1AA
-		 * which is then reflected in the CPUID register.
-		 */
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
-		msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	} else {
-		msr = rdmsr(MSR_MISC_PWR_MGMT);
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
-		msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
-		wrmsr(MSR_MISC_PWR_MGMT, msr);
-	}
-}
-
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -122,9 +97,6 @@ void soc_core_init(struct device *cpu)
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
-	/* Configure Intel Speed Shift */
-	configure_isst();
-
 	/* Enable PM timer emulation */
 	enable_pm_timer_emulation();