diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-04-24 17:42:49 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2020-05-04 22:46:21 +0000 |
| commit | 65cc80f740a736d3b947268c157d3331a7cec922 (patch) | |
| tree | 5850cf33b4017dd4f354f3dd8fbf83517ad8d307 /src/soc | |
| parent | 6ad8352a3de78e2f6869cc7fbc4274057fcffd4a (diff) | |
| download | coreboot-65cc80f740a736d3b947268c157d3331a7cec922.tar.xz | |
soc/intel/tigerlake: Update interrupt setting
Update interrupt setting based on latest FSP(3163.01)
Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer. Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.
Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/pci_irqs.asl | 4 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/irq.h | 15 |
2 files changed, 10 insertions, 9 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 62520b1f48..116b9a3fd0 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -19,6 +19,7 @@ Name (PICP, Package () { /* D31:HDA, SMBUS, TraceHUB */ Package(){0x001FFFFF, 3, 0, HDA_IRQ }, Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, + Package(){0x001FFFFF, 6, 0, GBE_IRQ }, Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, /* D30: UART0, UART1, SPI0, SPI1 */ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, @@ -64,8 +65,7 @@ Name (PICP, Package () { /* D18: ISH, SPI2 */ Package(){0x0012FFFF, 0, 0, ISH_IRQ }, Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* D16: CNVI_BT, TCH0, TCH1 */ - Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, + /* D16: TCH0, TCH1 */ Package(){0x0010FFFF, 6, 0, THC0_IRQ }, Package(){0x0010FFFF, 7, 0, THC1_IRQ }, /* D13: xHCI, xDCI */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 01ee10b4f4..8763abb903 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -11,20 +11,21 @@ #define PCH_IRQ11 11 #define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C1_IRQ 40 #define LPSS_I2C2_IRQ 29 #define LPSS_I2C3_IRQ 30 #define LPSS_I2C4_IRQ 31 #define LPSS_I2C5_IRQ 32 #define LPSS_SPI0_IRQ 36 #define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 18 -#define LPSS_SPI3_IRQ 23 -#define LPSS_UART0_IRQ 34 -#define LPSS_UART1_IRQ 35 +#define LPSS_SPI2_IRQ 34 +#define LPSS_SPI3_IRQ 43 +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 #define LPSS_UART2_IRQ 33 #define HDA_IRQ 16 +#define GBE_IRQ 16 #define SMBUS_IRQ 16 #define TRACEHUB_IRQ 16 @@ -49,8 +50,8 @@ #define CNVI_BT_IRQ 18 -#define THC0_IRQ 16 -#define THC1_IRQ 17 +#define THC0_IRQ 23 +#define THC1_IRQ 22 #define ISH_IRQ 16 |