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authorFurquan Shaikh <furquan@google.com>2020-05-16 21:46:41 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-20 00:35:25 +0000
commit66b9c0efb52f8953e52add59c70646fa1ce1b867 (patch)
treeb3f57be5af34e0a99cbe84e2e43070bb0bf5eea5 /src/soc
parent6dc858a01ffceb897b597607f2004b9aad2f0ae7 (diff)
downloadcoreboot-66b9c0efb52f8953e52add59c70646fa1ce1b867.tar.xz
soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/acpi/systemagent.asl8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl
index 74a25c15fb..258e6e7e7a 100644
--- a/src/soc/intel/broadwell/acpi/systemagent.asl
+++ b/src/soc/intel/broadwell/acpi/systemagent.asl
@@ -147,13 +147,17 @@ Method (_CRS, 0, Serialized)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
- Local0 = ^MCHC.TLUD
+ // Lower 20 bits of TOLUD register need to be masked since they contain lock and
+ // reserved bits.
+ Local0 = ^MCHC.TLUD & (0xfff << 20)
Local1 = ^MCHC.MEBA
// Check if ME base is equal
If (Local0 == Local1) {
// Use Top Of Memory instead
- Local0 = ^MCHC.TOM
+ // Lower 20 bits of TOM register need to be masked since they contain lock and
+ // reserved bits.
+ Local0 = ^MCHC.TOM & (0x7ffff << 20)
}
PMIN = Local0