diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2021-02-16 11:45:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:25:20 +0000 |
| commit | 81f70a9fdfe125afac0ef8673b97c2aff9b511da (patch) | |
| tree | b16c335d84063987c9f7c195dc8ac7d2f4c5fd12 /src/soc | |
| parent | 9b725cf31194d772b62d50f3653ad8772f31d0b6 (diff) | |
| download | coreboot-81f70a9fdfe125afac0ef8673b97c2aff9b511da.tar.xz | |
soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI device
There is no PCI host interface for Cnvi BT in Alderlake.
CNVi BT on Alderlake is an USB device.
Change-Id: I3e08c6d6f00e81267dc28c9b37b2dfff5cd75db1
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51352
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pci_devs.h | 2 |
2 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index cd9ebf9192..19411a6d20 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -60,7 +60,6 @@ chip soc/intel/alderlake device pci 0e.0 alias vmd off end device pci 10.0 alias thc0 off end device pci 10.1 alias thc1 off end - device pci 10.2 alias cnvi_bt off end device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 6a114ae61c..23cf24810d 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -73,10 +73,8 @@ #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 0) #define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 1) -#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) #define PCH_DEV_THC0 _PCH_DEV(SIO0, 0) #define PCH_DEV_THC1 _PCH_DEV(SIO0, 1) -#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) #define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) |