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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-04 19:51:17 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-12-09 14:23:31 +0000
commit8d187f4d22572fa01dabd46d994b3639eb83b382 (patch)
treea583f91062a5eb69f193663c23e014fe8194b39d /src/soc
parent8dcd62d705fb3058f7c36e554840c3df69f244ce (diff)
downloadcoreboot-8d187f4d22572fa01dabd46d994b3639eb83b382.tar.xz
soc/amd: Remove Kconfig X86_RESET_VECTOR
The architectural requirement is for the address to be located at the end of bootblock -0x10 bytes, so the definition was redundant with other Kconfig variables. Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/cezanne/Kconfig9
-rw-r--r--src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld6
-rw-r--r--src/soc/amd/picasso/Kconfig9
3 files changed, 3 insertions, 21 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 2a26d6d0e7..d2badc9ee5 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -61,15 +61,6 @@ config C_ENV_BOOTBLOCK_SIZE
This variable controls the DRAM allocation size in linker script
for bootblock stage.
-config X86_RESET_VECTOR
- hex
- depends on ARCH_X86
- default 0x203fff0
- help
- Sets the reset vector within bootblock where x86 starts execution.
- Reset vector is supposed to live at offset -0x10 from end of
- bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10.
-
config ROMSTAGE_ADDR
hex
default 0x2040000
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index e6de812b92..dae69d030f 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -84,7 +84,6 @@ SECTIONS
#if CONFIG(VBOOT)
PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
#endif
- _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
_ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
@@ -105,10 +104,11 @@ nullidt_offset = nullidt & 0xffff;
SECTIONS {
/* Trigger an error if I have an unusable start address */
- _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
+ _TOO_LOW = _X86_RESET_VECTOR - 0xfff0;
_bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
- . = CONFIG_X86_RESET_VECTOR;
+ . = CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10;
+ _X86_RESET_VECTOR = .;
.reset . : {
*(.reset);
. = 15;
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 79fc3be621..fcb7ddbed5 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -134,15 +134,6 @@ config C_ENV_BOOTBLOCK_SIZE
This variable controls the DRAM allocation size in linker script
for bootblock stage.
-config X86_RESET_VECTOR
- hex
- depends on ARCH_X86
- default 0x203fff0
- help
- Sets the reset vector within bootblock where x86 starts execution.
- Reset vector is supposed to live at offset -0x10 from end of
- bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10.
-
config ROMSTAGE_ADDR
hex
default 0x2040000