diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-06 12:53:33 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-16 11:07:16 +0000 |
commit | a1cc557d614c8ea6822c8dada5aeb049cf685826 (patch) | |
tree | e34be00ba12ffe474ee740ee9ea5c663220e1979 /src/soc | |
parent | c8e86de3feff539e863562f3d4d896815aff2e70 (diff) | |
download | coreboot-a1cc557d614c8ea6822c8dada5aeb049cf685826.tar.xz |
soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/intel/xeon_sp/acpi.c | 8 | ||||
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h | 12 | ||||
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/soc_util.c | 21 | ||||
-rw-r--r-- | src/soc/intel/xeon_sp/include/soc/util.h | 1 | ||||
-rw-r--r-- | src/soc/intel/xeon_sp/nb_acpi.c | 11 | ||||
-rw-r--r-- | src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h | 12 | ||||
-rw-r--r-- | src/soc/intel/xeon_sp/skx/soc_util.c | 21 |
7 files changed, 46 insertions, 40 deletions
diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 3b4b7133e4..fb4cd78dd6 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -93,20 +93,17 @@ unsigned long acpi_fill_madt(unsigned long current) /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ #if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif #if (CONFIG(SOC_INTEL_SKYLAKE_SP)) const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current); cur_index = 0; - ioapic_id = ioapic_ids[cur_index]; gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, 0, 0, ioapic_id, + current += add_madt_ioapic(current, 0, 0, PCH_IOAPIC_ID, hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, gsi_base); ++cur_index; @@ -117,9 +114,8 @@ unsigned long acpi_fill_madt(unsigned long current) &hob->PlatformData.IIO_resource[socket].StackRes[stack]; if (!is_iio_stack_res(ri)) continue; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; + ioapic_id = soc_get_iio_ioapicid(socket, stack); gsi_base = gsi_bases[cur_index]; uint32_t ioapic_base = ri->IoApicBase; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 68dee28a07..33e257cb7c 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -117,17 +117,5 @@ // ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 -#define PC00_IOAPIC_ID 0x09 -#define PC01_IOAPIC_ID 0x0A -#define PC02_IOAPIC_ID 0x0B -#define PC03_IOAPIC_ID 0x0C -#define PC04_IOAPIC_ID 0x0D -#define PC05_IOAPIC_ID 0x0E -#define PC06_IOAPIC_ID 0x0F -#define PC07_IOAPIC_ID 0x10 -#define PC08_IOAPIC_ID 0x11 -#define PC09_IOAPIC_ID 0x12 -#define PC10_IOAPIC_ID 0x13 -#define PC11_IOAPIC_ID 0x14 #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 578f67cda2..280bedcd77 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -63,3 +63,24 @@ int soc_get_stack_for_port(int port) else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index fc0dee7aba..2637017c89 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -16,6 +16,7 @@ const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); +uint8_t soc_get_iio_ioapicid(int socket, int stack); struct iiostack_resource { uint8_t no_of_stacks; diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 55c3d820ca..4a4498080a 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -184,15 +184,6 @@ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, const IIO_UDS *hob) { - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - uint32_t enum_id; unsigned long tmp = current; @@ -231,7 +222,7 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, } // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + enum_id = soc_get_iio_ioapicid(socket, stack); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index b500c2896c..02df790460 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -161,17 +161,5 @@ // ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 -#define PC00_IOAPIC_ID 0x09 -#define PC01_IOAPIC_ID 0x0A -#define PC02_IOAPIC_ID 0x0B -#define PC03_IOAPIC_ID 0x0C -#define PC04_IOAPIC_ID 0x0D -#define PC05_IOAPIC_ID 0x0E -#define PC06_IOAPIC_ID 0x0F -#define PC07_IOAPIC_ID 0x10 -#define PC08_IOAPIC_ID 0x11 -#define PC09_IOAPIC_ID 0x12 -#define PC10_IOAPIC_ID 0x13 -#define PC11_IOAPIC_ID 0x14 #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 7d95ae8600..b903249e1d 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -148,3 +148,24 @@ int soc_get_stack_for_port(int port) else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} |