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authorLijian Zhao <lijian.zhao@intel.com>2018-09-25 14:27:50 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-09-28 09:55:22 +0000
commita57447da085ee0f534df0b9c73aac83aafb6f6e3 (patch)
tree00c1b3a4900417f30597b66760180dbd22d185b1 /src/soc
parentdc20a7d45d45bc52ce0c3e0dab0e06b328109075 (diff)
downloadcoreboot-a57447da085ee0f534df0b9c73aac83aafb6f6e3.tar.xz
soc/intel/cannonlake: Move SkipMpInit config to FSPM
SkipMpInit UPD had ben moved from Fsp SiliconInit UPD to Fsp MemoryInit UPD, hence change the settings in coreboot side as well. The old options in SiliconInit get deprecated, so leave the code as is will be harmless. Make the changes limited to coffeelake itself. Change-Id: If968de78117068668e4f0006c412442c50658ba9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28740 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index ae1ba4d7d0..8bdabbf803 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -22,6 +22,7 @@
#include <compiler.h>
#include <console/console.h>
#include <fsp/util.h>
+#include <intelblocks/chip.h>
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
#include <memory_info.h>
@@ -175,6 +176,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->VmxEnable = 0;
else
m_cfg->VmxEnable = config->VmxEnable;
+#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
+ m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
+#endif
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)