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authorAngel Pons <th3fanbus@gmail.com>2020-07-13 01:12:57 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-20 13:22:13 +0000
commitb74975e40364ce3b66bda54167ca20cdf6cbda35 (patch)
treec5e39e0e418f107f35f389b75be7b0b0d32487a9 /src/soc
parenta208c6ce732a58c44bb2bf105d5e664f0887d5fe (diff)
downloadcoreboot-b74975e40364ce3b66bda54167ca20cdf6cbda35.tar.xz
soc/amd/stoneyridge: Select HAVE_CF9_RESET
Looks like some preparation is needed before reset. However, Picasso also needs some special handling and still selects this option without selecting HAVE_CF9_RESET_PREPARE. So, just add HAVE_CF9_RESET for now. Change-Id: I0c6da9a43a28dbee916fd6bda9ae380ebd619edf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43388 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index f093e28670..b29bd990db 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS
select GENERIC_GPIO_LIB
select GENERIC_UDELAY
select IOAPIC
+ select HAVE_CF9_RESET
select HAVE_USBDEBUG_OPTIONS
select SOC_AMD_COMMON_BLOCK_SPI
select TSC_SYNC_LFENCE