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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-05-12 18:44:30 +0530 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2021-05-16 22:17:26 +0000 |
| commit | c4813ea2604600476fa3c95557135b3225f404aa (patch) | |
| tree | 4f13dec38bea020a08663399669c34135c023860 /src/soc | |
| parent | 3704c65f08aa56e252cee9bf0b90d9173b20204c (diff) | |
| download | coreboot-c4813ea2604600476fa3c95557135b3225f404aa.tar.xz | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00
The headers added are generated as per FSP v2162_00.
Previous FSP version was v2117_00.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Remove DisableDimmMc*Ch* Upds in FspmUpd.h
- Add DisableMc*Ch* Upds in FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid
compilation failure other change related to UPDs name change will be
part of next patch in relation chain.
BUG=b:187189546
BRANCH=None
TEST=Build and boot ADLRVP using all the patch in relation chain.
Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e
Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913
Cq-Depend: chromium:TODO
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/meminit.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 33f26da87f..2c46b07ec5 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -133,14 +133,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, }; uint8_t *disable_dimm_upds[MRC_CHANNELS] = { - &mem_cfg->DisableDimmMc0Ch0, - &mem_cfg->DisableDimmMc0Ch1, - &mem_cfg->DisableDimmMc0Ch2, - &mem_cfg->DisableDimmMc0Ch3, - &mem_cfg->DisableDimmMc1Ch0, - &mem_cfg->DisableDimmMc1Ch1, - &mem_cfg->DisableDimmMc1Ch2, - &mem_cfg->DisableDimmMc1Ch3, + &mem_cfg->DisableMc0Ch0, + &mem_cfg->DisableMc0Ch1, + &mem_cfg->DisableMc0Ch2, + &mem_cfg->DisableMc0Ch3, + &mem_cfg->DisableMc1Ch0, + &mem_cfg->DisableMc1Ch1, + &mem_cfg->DisableMc1Ch2, + &mem_cfg->DisableMc1Ch3, }; size_t ch, dimm; |