diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-05-10 17:02:58 -0600 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2021-05-14 01:02:24 +0000 |
| commit | cdbedb680be3433b007e032eac8e9ce9540ad92f (patch) | |
| tree | e1b14f8b0c0c742166072581246e567e769e3d5a /src/soc | |
| parent | 40acfe7f77304386fa1835faab8d0cd1a132deb6 (diff) | |
| download | coreboot-cdbedb680be3433b007e032eac8e9ce9540ad92f.tar.xz | |
soc/amd/cezanne: Enable GFX HDA FSP UPD
By default, FSP disables the GFX HDA. Enable it to support HDMI Audio
functionality.
BUG=b:186479763
TEST=Build and boot to OS in guybrush. Ensure that the GFX HDA is
enumerated in lspci output.
04:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device 1637
Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54100
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 4aff7e09bb..5dd3056f0c 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -8,10 +8,34 @@ #include <device/device.h> #include <fsp/api.h> #include <soc/platform_descriptors.h> +#include <soc/pci_devs.h> #include <string.h> #include <types.h> #include "chip.h" +static const struct device_path gfx_hda_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_ABC_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = GFX_HDA_DEVFN + }, +}; + +static bool devtree_gfx_hda_dev_enabled(void) +{ + const struct device *gfx_hda_dev; + + gfx_hda_dev = find_dev_nested_path(pci_root_bus(), gfx_hda_path, + ARRAY_SIZE(gfx_hda_path)); + if (!gfx_hda_dev) + return false; + + return gfx_hda_dev->enabled; +} + static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, const fsp_dxio_descriptor *descs, size_t num) { @@ -136,6 +160,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->telemetry_vddcrsocOffset = config->telemetry_vddcrsocoffset; + mcfg->enable_nb_azalia = devtree_gfx_hda_dev_enabled(); + fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); } |