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authorpchandri <preetham.chandrian@intel.com>2015-09-14 14:11:38 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-10-27 15:15:30 +0100
commite57e72681fa218bb747f658576c64111c20363e3 (patch)
tree380bf4a6c7488c2c5f3b0818289d7e152c2a7e69 /src/soc
parentb45dde0b78cbe646e12316408ac67cdc72ed9a9d (diff)
downloadcoreboot-e57e72681fa218bb747f658576c64111c20363e3.tar.xz
intel/kunimitsu Fab3: Strengthening Rcomp target CTRL value
This patch strengthens the Rcomp Target CTRL by 10% for 8GB memory part K4E6E304EE-EGCF as with the current values the MRC training is failing due to more load on CS# BRANCH=None BUG=chrome-os-partner:44647 TEST=BUilds and boots on Kunimitsu. Change-Id: I478002bbebabaac418356d4b5b4755bb56009268 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b208659e690d8cb5b8dcaf30eed53c01b9f77f6d Original-Change-Id: Ia0a0c1358649af77a3a0d301cb791f26f1e039bf Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304103 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/12143 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/include/soc/pei_data.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
index 2773051c03..be8ba79b92 100644
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ b/src/soc/intel/skylake/include/soc/pei_data.h
@@ -91,6 +91,7 @@ struct pei_data {
/* Data from MRC that should be saved to flash */
void *data_to_save;
int data_to_save_size;
+ int mem_cfg_id;
} __attribute__((packed));
typedef struct pei_data PEI_DATA;