summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-10-27 13:35:54 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-22 04:17:03 +0100
commitebc21d125fb83ebde6af326df74789c51a48550a (patch)
treec76ac31f3ae1f4651a65c99d577b70ad27be5b57 /src/soc
parentbac0fad4082036638b30506a27fbe62c6e71b237 (diff)
downloadcoreboot-ebc21d125fb83ebde6af326df74789c51a48550a.tar.xz
intel/sch: Switch to MMCONF_SUPPORT_DEFAULT
Untested, only affected board is iwave/iwRainbowG6. Change-Id: Ie3c40ede85c9f89b54804dd2a411645be93911bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17528 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/sch/Kconfig4
-rw-r--r--src/soc/intel/sch/bootblock.c38
-rw-r--r--src/soc/intel/sch/early_init.c3
3 files changed, 42 insertions, 3 deletions
diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig
index 6bbb168782..e97d6b3629 100644
--- a/src/soc/intel/sch/Kconfig
+++ b/src/soc/intel/sch/Kconfig
@@ -25,6 +25,10 @@ config SOC_INTEL_SCH
if SOC_INTEL_SCH
+config BOOTBLOCK_NORTHBRIDGE_INIT
+ string
+ default "soc/intel/sch/bootblock.c"
+
config VGA_BIOS_ID
string
default "8086,8108"
diff --git a/src/soc/intel/sch/bootblock.c b/src/soc/intel/sch/bootblock.c
new file mode 100644
index 0000000000..deff35e4e5
--- /dev/null
+++ b/src/soc/intel/sch/bootblock.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+/* Copy the bare minimum from port_access.c to enable MMCONF. */
+
+#define MSG_OPCODE_READ 0xD0000000
+#define MSG_OPCODE_WRITE 0xE0000000
+
+#define MCR 0xD0
+#define MDR 0xD4
+
+static void sch_port_access_write(int port, int reg, int bytes, long data)
+{
+ pci_io_write_config32(PCI_DEV(0, 0, 0), MDR, data);
+ pci_io_write_config32(PCI_DEV(0, 0, 0), MCR,
+ (MSG_OPCODE_WRITE | (port << 16) | (reg << 8)));
+ pci_io_read_config32(PCI_DEV(0, 0, 0), MDR);
+}
+
+static void bootblock_northbridge_init(void)
+{
+ /* Enable PCI MMCONF decoding BAR. */
+ sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */
+ sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
+}
diff --git a/src/soc/intel/sch/early_init.c b/src/soc/intel/sch/early_init.c
index ccc8022246..cd777769f2 100644
--- a/src/soc/intel/sch/early_init.c
+++ b/src/soc/intel/sch/early_init.c
@@ -196,9 +196,6 @@ static void sch_setup_non_standard_bars(void)
/* Base of Stolen Memory Address 0x1080 size 64B */
pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000);
- sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */
- sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
-
/* RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0,
((uintptr_t)DEFAULT_RCBABASE | 1));