diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-11-29 15:06:26 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-13 13:01:33 +0200 |
| commit | f9ff353430aae70e5cc04fb32d983b572956bd7d (patch) | |
| tree | bd8e41ccc824d0510e6872063b769ab4d6ab7fdf /src/soc | |
| parent | 038cce2c2ec540163563a42c784f1c32564ee1b4 (diff) | |
| download | coreboot-f9ff353430aae70e5cc04fb32d983b572956bd7d.tar.xz | |
spi: support controllers with limited transfer size capabilities
Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI
read and write transactions. Limiting transfer size in the wrapper
allows to provide the API user with unlimited transfer size
transactions.
The tranfer size limitation is added to the spi_slave structure, which
is set up by the controller driver. The value of zero in this field
means 'unlimited transfer size'. It will work with existion drivers,
as they all either keep structures in the bss segment, or initialize
them to all zeros.
This patch addresses the problem for reads only, as coreboot is not
expected to require to write long chunks into SPI devices.
BRANCH=none
BUG=chrome-os-partner:32441, chrome-os-partner:31438
TEST=set transfer size limit to artificially low value (4K) and
observed proper operation on both Pistachio and ipq8086: both
Storm and Urara booted through romstage and ramstage.
Change-Id: Ibb96aa499c3eec458c94bf1193fbbbf5f54e1477
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4f064fdca5b6c214e7a7f2751dc24e33cac2ea45
Original-Change-Id: I9df24f302edc872bed991ea450c0af33a1c0ff7b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232239
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9571
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/imgtec/pistachio/spi.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index 69682d0456..5522f2408e 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -25,6 +25,9 @@ #error "Unsupported SPI driver API" #endif +/* Imgtec controller uses 16 bit packet length. */ +#define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) + struct img_spi_slave { struct spi_slave slave; /* SPIM instance device parameters */ @@ -441,6 +444,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) slave->bus = bus; slave->cs = cs; slave->rw = SPI_READ_FLAG | SPI_WRITE_FLAG; + slave->max_transfer_size = IMGTEC_SPI_MAX_TRANSFER_SIZE; + device_parameters->bitrate = 64; device_parameters->cs_setup = 0; device_parameters->cs_hold = 0; |