diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-27 08:23:15 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-01 14:30:45 +0000 |
| commit | fc458cdc5374a293483455acdd42cdbdd032ae27 (patch) | |
| tree | 41659c036bc61e28137ce574c99eb2bf2c675441 /src/soc | |
| parent | 87471366e42106b136d6cd0fba008b8c7eb53f85 (diff) | |
| download | coreboot-fc458cdc5374a293483455acdd42cdbdd032ae27.tar.xz | |
amd/stoneyridge: Create gnvs entries for AOAC devices
A later patch will leverage AMD's ASL support for handling AOAC
devices. This will gather coreboot's device enables from a bitwise field,
where each bit corresponds to the register offset used to control
each devices.
Create an identical structure, and add it to the nvs ASL and global_nvs_t
structure.
BUG=b:77602074
Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/globalnvs.asl | 19 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/nvs.h | 5 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 21 |
3 files changed, 44 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index ba50e3874d..810c97b9e4 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -47,6 +47,25 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TCRT, 8, // 0x2E - Critical Threshold TPSV, 8, // 0x2F - Passive Threshold TMAX, 8, // 0x30 - CPU Tj_max + Offset (0x34), // 0x34 - AOAC Device Enables + , 5, + IC0E, 1, // I2C0, 5 + IC1E, 1, // I2C1, 6 + IC2E, 1, // I2C2, 7 + IC3E, 1, // I2C3, 8 + , 2, + UT0E, 1, // UART0, 11 + UT1E, 1, // UART1, 12 + , 2, + ST_E, 1, // SATA, 15 + , 2, + EHCE, 1, // EHCI, 18 + , 4, + XHCE, 1, // XCHI, 23 + SD_E, 1, // SD, 24 + , 2, + ESPI, 1, // ESPI, 27 + , 4, /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index bcac3a9d8c..dfc10a2e25 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -28,6 +28,7 @@ #include <compiler.h> #include <stdint.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <soc/southbridge.h> typedef struct global_nvs_t { /* Miscellaneous */ @@ -50,7 +51,9 @@ typedef struct global_nvs_t { uint8_t tcrt; /* 0x2E - Critical Threshold */ uint8_t tpsv; /* 0x2F - Passive Threshold */ uint8_t tmax; /* 0x30 - CPU Tj_max */ - uint8_t unused[207]; + uint8_t pad1[3]; + aoac_devs_t aoac; /* 0x34 - AOAC device enables */ + uint8_t unused[200]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f054b3b61e..c54a7d43cc 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -400,6 +400,27 @@ struct stoneyridge_aoac { int status; }; +typedef struct aoac_devs { + unsigned int :5; + unsigned int ic0e:1; /* 5: I2C0 */ + unsigned int ic1e:1; /* 6: I2C1 */ + unsigned int ic2e:1; /* 7: I2C2 */ + unsigned int ic3e:1; /* 8: I2C3 */ + unsigned int :2; + unsigned int ut0e:1; /* 11: UART0 */ + unsigned int ut1e:1; /* 12: UART1 */ + unsigned int :2; + unsigned int st_e:1; /* 15: SATA */ + unsigned int :2; + unsigned int ehce:1; /* 18: EHCI */ + unsigned int :4; + unsigned int xhce:1; /* 23: xHCI */ + unsigned int sd_e:1; /* 24: SDIO */ + unsigned int :2; + unsigned int espi:1; /* 27: ESPI */ + unsigned int :4; +} __packed aoac_devs_t; + struct soc_power_reg { uint16_t pm1_sts; uint16_t pm1_en; |