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| author | zbao <fishbaozi@gmail.com> | 2012-04-05 13:18:49 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-12 00:14:58 +0200 |
| commit | 9bcdbf8eaa0c73d130ba555163f89fa1759c8c99 (patch) | |
| tree | c8d480f7e75444037a5ba491ea3987282e2faa21 /src/southbridge/amd/cimx/sb800/early.c | |
| parent | 2c2e78d845cd28eb3b11c87fa3feafaf836cda7a (diff) | |
| download | coreboot-9bcdbf8eaa0c73d130ba555163f89fa1759c8c99.tar.xz | |
Add Southbridge support for S3.
1. Add some CIMX call for S3.
2. Detect sleep type.
Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/621
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/early.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/early.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 9d49a52d54..f692897dcc 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -23,9 +23,11 @@ #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ #include <arch/romcc_io.h> /* device_t */ +#include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#include "cbmem.h" #if CONFIG_RAMINIT_SYSINFO == 1 @@ -80,3 +82,9 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_is_wakeup_early(void) +{ + return (acpi_get_sleep_type() == 3); +} +#endif |