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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-02-03 13:49:24 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-03 13:49:24 +0000 |
| commit | 5a559d4386b4f659bfeddffa8f38670e24a35ac0 (patch) | |
| tree | 2ba497b765b18431b6018af28fc80df360fe71f7 /src/southbridge/amd/cs5536/cs5536_early_setup.c | |
| parent | fa742da56be11090fc713c21bc3faf786d99b135 (diff) | |
| download | coreboot-5a559d4386b4f659bfeddffa8f38670e24a35ac0.tar.xz | |
The UART2 on the AMD cs5536 is incorrectly configured in two places.
GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive (compound fault).
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Edwin Beasant <edwin_beasant@virtensys.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536/cs5536_early_setup.c')
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536_early_setup.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c index d16bac9208..7c67d1f042 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_setup.c +++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c @@ -172,6 +172,7 @@ static void cs5536_setup_onchipuart(void) outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + /* GPIO9 - UART1_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); |